1. Field of the Invention
This invention generally relates to the formation of electrical junctions in semiconductors and more particularly to the formation of very shallow junctions with controlled dopant concentration and junction depth.
2. Description of the Prior Art
The formation of very shallow electrical junctions, e.g., less than about 0.2 .mu.m deep, is currently a limiting factor in the development of advanced silicon integrated circuits. Such very shallow junctions can be formed when a p-type or n-type dopant is introduced into the surface of a semiconductor of the opposite conductivity type. Such p-n or n-p junctions may be used, for example, in the formation of the source and drain of insulated-gate field-effect transistors or in the formation of the base and emitter of bipolar junction transistors.
In certain bipolar junction transistor processes, a shallow, lightly doped junction is often used to form a link between an active intrinsic base region and the extrinsic base contact region. Shallow junctions may also be used to control the conductivity of sidewalls in trenches and other features formed in silicon.
Junctions in silicon surfaces have conventionally been formed by many techniques including ion implantation, doped glass and vapor diffusion. One of the limitations of ion implantation is the difficulty of achieving sufficiently precise depth control to reliably form very shallow junctions. The doped glass technique achieves the desired shallow junction depth but may not provide the needed range of dopant concentrations. Moreover, neither the ion implant nor the doped glass technique is normally considered suitable for creating shallow junctions on a semiconductor feature having a narrow opening, such as a deep trench.
Conventional vapor diffusion techniques have been considered for use in forming electrical junctions, including the two zone furnace process and the closed box process. Both of these techniques, which are discussed in more detail below, are typically limited to forming junctions with high dopant concentrations.
In the ion implantation method, dopant atoms of the appropriate type are ionized and accelerated toward a semiconductor surface, typically silicon. The ions penetrate the lattice of the silicon atoms to a degree determined by the ion energy, the ion mass, the orientation of the lattice relative to the ion beam, and the degree of crystallinity of the silicon. This technique offers good dopant control and good uniformity across the semiconductor surface, but it is often very difficult to control the depth of shallow junctions formed by this technique.
As stated above, one factor determining the depth of penetration of the dopant ions is the mass of the ions used. Ions having a higher mass, such as arsenic, are more controllable than ions having a lower mass, such as boron. Boron ions are preferred, but they experience less energy loss when passing through crystalline silicon and tend to channel into the spaces between adjacent atoms in the lattice. This results in the boron ions forming a deeper and poorly controlled junction.
Several approaches have been proposed to avoid the channeling effect of boron ions: misorienting the semiconductor surface relative to the ion beam; randomizing the ion beam by covering the surface with an amorphous film such as silicon dioxide; and randomizing the lattice by the implantation of a heavy ion such as germanium, tin or antimony, to create an amorphous layer of silicon on the surface of the semiconductor. With the last described approach, the amorphous layer may be recrystallized during a subsequent heat treatment to restore the lattice and activate the dopant.
Although these approaches have achieved some success in the formation of very shallow junctions using boron, these conventional approaches suffer from drawbacks. The first approach of misorienting the semiconductor surface relative to the ion beam is not completely effective. A small percentage of the boron atoms still tend to channel even at large angles. The second approach of covering the surface with an amorphous film suffers from a similar limitation, unless a comparatively thick film layer is used, in which case depth control is poor.
The third approach of implanting heavy ions requires an extra implantation step, using ions not conveniently available in production implanters. Further, the use of germanium or tin ions can result in defect structures which do not anneal out completely during the subsequent heat treatment. The use of antimony ions minimizes this problem, but antimony acts as an n-type dopant which adversely affects the resistivity control of the final doped region. Further, the presence of antimony requires higher concentrations of boron ions to achieve a given carrier concentration, limiting the use of antimony to relatively heavily doped junctions.
The second technique currently used for forming shallow junctions in silicon, drives in the dopant from a doped glass. A doped glass, as will be described below in greater detail, is formed on the surface of the silicon. The glass formation is followed by a heat treatment which drives the dopant out of the glass into the silicon. This technique allows comparatively good control of dopant dose and uniformity, at high dopant concentrations, and is usable in forming reasonably shallow junctions.
However, it is difficult to control the dopant concentration at lower concentration levels because the concentration changes greatly with only a slight change in the heat treatment temperature. A further drawback of this technique is that it requires extra processing steps.
During this technique, doped glass is typically formed on the silicon surface by introducing a dopant-containing gas into a high-temperature reaction furnace. The gas is reacted with oxygen either by itself to form an oxide of the dopant, for example B.sub.2 O.sub.3, or with a silicon containing gas such as silane to form a doped silicate glass on the surface of the semiconductor. Subsequent heating of the coated semiconductor surface results in diffusion of the dopant from the glass into the semiconductor. Dopant control is achieved by controlling the concentration of the dopant in the ambient gas from which the doped glass is formed and by varying the temperature and pressure within the furnace. After the diffusion step, the doped glass may be removed from the semiconductor surface.
One disadvantage of this technique results from the difficulty in controlling dopant concentrations. At dopant concentrations below the solid solubility of the dopant in silicon at the diffusion temperature, relatively minute changes in temperature result in significant changes in the concentration of the dopant diffused into the semiconductor surface.
This typically limits the reproducibility of this method to concentrations at or near the solubility of the dopant in silicon, typically about 1.times.10.sup.20 cm.sup.-3. Such high concentrations inhibit reliable formation of very shallow junctions because of concentration dependent diffusivity and other effects.
Another disadvantage of this technique is that extra processing steps are required prior to the diffusion of the dopant into the semiconductor surface. Thin oxides such as the native oxide of silicon are commonly found on the surface of silicon semiconductors. Such thin oxides significantly reduce dopant diffusion from certain doped glasses, for example, borosilicate glass. The controlled precleaning required to remove such oxides is difficult to achieve in conjunction with the typical doped glass process.
A further disadvantage of both the ion implantation and the doped glass techniques is their limitations as to the type of surface features for which they are appropriate. For example, they are not readily suitable for doping the sidewalls of a deep trench, found in a semiconductor by, e.g., local etching of the semiconductor surface.
The ion implantation technique is essentially a line-of-sight method. If the area to be doped is "visible" to the ion source, it can be implanted. Trench sidewalls, however, present an extremely small surface area to incoming ions, creating great difficulty in controlling the ion dosage. Control of the ion dose per unit area of the sidewall is aggravated by variations in the angle of the sidewall to the ion beam.
Such variations may be caused by variation of the sidewall slope introduced during etching, shifts in orientation of the surface relative to the beam during placement in the implanter, and variation in the beam angle due to scanning of the beam across the surface. The typical results of ion implantation at slight angles onto a wafer with significant surface topography are non-uniform doped regions and regions without dopant.
Use of the doped glass technique to dope the sidewalls of a deep trench also often produces unsatisfactory results. As described above, doped glass may be formed by reacting a dopant containing gas with an oxidizer to form an oxide of the dopant. This oxide is then deposited on the surface of the semiconductor. However, depletion of reactants typically causes oxide deposition and dopant concentration to vary as a function of depth within a trench.
As noted above, various vapor diffusion techniques have also been used to form electrical junctions. One such technique is known as the two zone furnace process. This technique utilizes a furnace having two individually controllable heat zones. A dopant source is placed in the first zone, and a semiconductor surface is placed in the second zone. A slightly oxidizing gas is passed through the furnace and transports the vapor from the dopant source in the first zone to the semiconductor surface in the second zone. This process typically produces a doped oxide on the surface of the semiconductor. The first zone controls the vapor pressure of the dopant and can be eliminated if the dopant source used is sufficiently volatile at room temperature.
This technique has been used with reasonable success to produce junctions with dopant concentrations at or near the solid solubility of the dopant in silicon at the diffusion temperature. At lower concentrations, a relatively minute change in temperature results in significant changes in the concentration of the dopant diffused into the semiconductor surface. This limits the reproducibility of the two zone technique to high surface concentrations of dopant in the semiconductor.
Another vapor diffusion approach is known as the closed box technique. This technique utilizes a closed box containing a semiconductor surface and a dopant source. The dopant source is a solution of the oxide of the dopant in silicon dioxide. When the box is heated to diffusion temperature, it fills with the vapors of the dopant. The dopant then diffuses into the semiconductor surface.
This approach is limited because the system cannot approach a satisfactory near-equilibrium condition except when the box is saturated with the dopant. With such high concentrations of the dopant in the box, the dopant concentration in the semiconductor saturates at the maximum solid solubility of the dopant in silicon at the diffusion temperature. Thus, this method also is typically limited to high concentrations of dopant in the semiconductor.
What is needed therefore is a technique for forming very shallow electrical junctions which have a wider range of surface concentrations than are conveniently available with conventional methods. The technique should be adaptable for use with a wide range of semiconductor features having narrow openings, such as deep trenches. The needed technique should avoid the problems of conventional techniques, such as the channeling of the ion implantation method and the high concentration limitation of the doped glass and vapor diffusion techniques.